METHOD OF FORMING A CMOS STRUCTURE HAVING GATE INSULATION FILMS OF DIFFERENT THICKNESSES

Number of patents in Portfolio can not be more than 2000

United States of America Patent

SERIAL NO

14828281

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
TESSERA ADVANCED TECHNOLOGIES INCSAN JOSE CA

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
HORIGUCHI, Masashi Kanagawa-ken, JP 190 3754
MATSUZAKI, Nozomu Tokyo, JP 78 1592
MIZUNO, Hiroyuki Tokyo, JP 291 3429

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation