Neutralization of parasitic capacitance using MOS device
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United States of America Patent
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Nov 8, 2016
Grant Date -
Dec 3, 2015
app pub date -
May 27, 2014
filing date -
May 27, 2014
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Abstract
An apparatus comprises an amplifier comprising at least one metal oxide semiconductor (MOS) transistor having a parasitic gate-to-drain capacitance, and at least one MOS neutralization device having a neutralization capacitance configured to compensate for the parasitic gate-to-drain capacitance of the at least one MOS transistor.
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