METHOD AND SYSTEM FOR A GALLIUM NITRIDE VERTICAL JFET WITH SELF-ALIGNED SOURCE AND GATE
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United States of America Patent
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app pub date -
Jul 30, 2015
filing date -
Aug 4, 2011
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Abstract
A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.
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