IO AND PVT CALIBRATION USING BULK INPUT TECHNIQUE
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United States of America Patent
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Issued Date -
Nov 19, 2015
app pub date -
May 16, 2014
filing date -
May 16, 2014
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Abandoned
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Abstract
The present invention discloses an efficient way to match the impedance between a pull-up path and a pull-down path of an IO cell without using stacked devices on the output stage of the IO cell to save area and to achieve higher speed; back-gate (bulk or body) voltages of a pull-up transistor and a pull-down transistor of the IO cell can be respectively adjusted to a value to achieve the desired impedance values of the pull-up and pull-down paths. A central calibration unit can generate an impedance calibration code and distribute them to a local adjustable bias generator in each IO cell groups, wherein the local adjustable bias generator, which is embedded in a power or a ground pad, receives the impedance calibration code and generates bias voltages to the back-gates of the pull-up and pull-down transistors for setting impedance values of the pull-up and pull-down paths, respectively.
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