Controlling Gate Formation for High Density Cell Layout

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United States of America Patent

SERIAL NO

14752320

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Abstract

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Methods of forming a semiconductor structure and the semiconductor structure are disclosed. In one embodiment, a semiconductor structure includes a substrate having a first active region, a second active region, and an insulating region separating the first and the second active regions. The structure further includes a vertical gate structure extending over the first and the second active regions and the insulating region, and a horizontal gate structure extending over the insulating region between the first and the second active regions.

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Patent Owner(s)

Patent OwnerAddress
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD8 LI-HSIN RD 6 HSINCHU SCIENCE PARK HSINCHU 300-78

International Classification(s)

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  • 2015 Application Filing Year
  • H01L Class
  • 25498 Applications Filed
  • 22451 Patents Issued To-Date
  • 88.06 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances20152016201720182019202020212022202320240255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Kuei Shun Hsinchu City, TW 50 594
Chuang, Harry Hak-Lay Singapore, SG 56 1050
Kuo, Cheng-Cheng Hsinchu City, TW 35 328
Liu, Chia-Chu Shin-Chu City, TW 46 509
Mii, Yuh-Jier Hsin-Chu, TW 29 661
Tsai, Tsung-Chieh Chu-Bei City, TW 43 165
Young, Bao-Ru Zhubei City, TW 184 1645

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Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges1377800619237183722181459473474314501 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05001000150020002500300035004000450050005500600065007000750080008500

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