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Abstract

An unified power management scheme for all the idle subsystems during normal mode of operation and power save mode of operation reduces significant power and time during saving and restoring context of System on a chip (SoC). Power management schemes based on subset of manufacturing tests and high speed non-volatile memory provides transparency and shortest latency of entering and exiting power save mode and as a result providing significant power savings and extending battery life. Due to the shortest logic delays in some phases of logic scan, memory BIST and analog BIST, entry procedure and exit procedures from power save mode consume least amount of time with little overhead due to clock switching and power gating procedures. Any part of SoC that can be tested during manufacture using standard procedures of logic scan, memory BIST, analog BIST and boundary scan will be able to enter and exit power save mode and still retain the state. By enabling power to the functional units only while they are performing a function prolongs the duration of normal operation with a single charging of the battery for mobile and portable devices.

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First Claim