Processor subroutine cache
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United States of America Patent
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Aug 11, 2020
Grant Date -
Oct 8, 2015
app pub date -
Apr 4, 2014
filing date -
Apr 4, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
A processor includes an execution unit and a subroutine cache. The execution unit is configured to execute instructions. The subroutine cache us configured to provide instructions of a subroutine to the execution unit for execution. The subroutine cache includes subroutine instruction storage, a subroutine address register, and subroutine cache control logic. The subroutine control logic is configured to: identify a subroutine call instruction provided to the execution unit; determine whether an instruction of a subroutine invoked by the subroutine call instruction is stored in the subroutine instruction storage by evaluating a subroutine validity indicator that indicates whether at least a portion of the subroutine is stored in the subroutine instruction storage; and provide the instruction of the subroutine to the execution unit based on the subroutine validity indicator indicating that at least a portion of the subroutine is stored in the subroutine instruction storage.
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