Current regulation for accurate and low-cost voltage measurements at the wafer level
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United States of America Patent
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Jun 30, 2020
Grant Date -
Oct 1, 2015
app pub date -
Mar 26, 2014
filing date -
Mar 26, 2014
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Abstract
A test system and test techniques for accurate high current parametric testing of semiconductor devices. In operation, the test system supplies a current to the semiconductor device and measures a voltage on the device. The testing system may use the measured voltage to compute an ON resistance for the high-current semiconductor device. In one technique, multiple force needles contact a pad in positions that provide equi-resistant paths to one or more sense needles contacting the same pad. In another technique, current flow through the force needles is regulated such that voltage at the pad of the device under test is representative of the ON resistance of the device and independent of contact resistance of the force needle. Another technique entails generating an alarm indication when the contact resistance of a force needle exceeds a threshold.
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