Ultra Low Power Transistor for 40nm Processes
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
N/A
Issued Date -
Sep 24, 2015
app pub date -
Dec 4, 2014
filing date -
Mar 24, 2014
priority date (Note) -
Abandoned
status (Latency Note)
Importance
Abstract
Methods of fabricating ultra-low power transistors are described using advanced technology nodes (e.g. 40 nm or less). In an embodiment, by optimizing a MOSFET to a different point, i.e. for low junction off (or leakage) current rather than speed/on current, a MOSFET can be produced which still meets the HCl reliability specification but has significantly reduced power consumption when off, e.g. half to one third of the standard off current. At this new optimisation point, the LDD dose is reduced to a level (e.g. 10-20% of the standard LDD dose) such that if it is reduced further, the device will no longer pass the HCl reliability specification. This is in contrast to standard MOSFETs which are optimized for speed/on current and have an LDD dose which, if increased further, would cause the device to no longer pass the HCl reliability specification.
First Claim
Other Claims data not available