Fault and Variation Tolerant Energy and Area Efficient Links for Network-on-Chips
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Sep 17, 2015
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May 13, 2015
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Apr 4, 2008
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Abstract
The present invention provides methods for detecting and correcting transmission errors in inter-router links of Network-on-Chip (NoC) architectures. A NoC has repeaters along its bus lines. The output of a main repeater is compared and multiplexed with the output of a shadow repeater. If these outputs are the same the multiplexer outputs the output of the main repeater, otherwise an error is detected and the multiplexer outputs the output of the shadow repeater.
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