METHOD IN A PROCESSOR, AN APPARATUS AND A COMPUTER PROGRAM PRODUCT
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United States of America Patent
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Issued Date -
Sep 17, 2015
app pub date -
Mar 21, 2012
filing date -
Mar 21, 2012
priority date (Note) -
Abandoned
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Abstract
There is disclosed a method in which a pipelining instruction is received by a first processor core of a multicore processor. Information in the pipelining instruction is used to determine a connection between a first functional unit in the first processor core and a second functional unit in a second processor core of the multicore processor. A switch is controlled to form a pipeline comprising the first functional unit and the second functional unit to enable data communication connection between an output of the first functional unit and an input of the second functional unit. The method may further comprise using a translation unit to translate an instruction of an instruction set of a first processor core to a corresponding instruction or a sequence of instructions of an instruction set of the second processor core. There is also disclosed an apparatus and a computer program product to implement the method.
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