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United States of America Patent

APP PUB NO 20150255930A1
SERIAL NO

14197202

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Abstract

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An interface for protecting electronic devices from external Electric Over-Stress (EOS), Electromagnetic Interference (EMI) and Electrostatic Discharge (ESD) is disclosed. The interface is coupled to a PCB having electronic circuits. The interface device comprises a plurality of conducting lines for establishing electrical communication with the circuits on the PCB, wherein each conducting line has a distinct potential; and protection components connected to the conducting lines in the interface to shunt the EOS/EMI/ESD energy therethrough in the event of EOS occurring on the conducting lines.

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Patent Owner(s)

Patent OwnerAddress
ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED475 OAKMEAD PARKWAY SUNNYVALE CA 94085

International Classification(s)

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  • 2014 Application Filing Year
  • H01R Class
  • 2939 Applications Filed
  • 2751 Patents Issued To-Date
  • 93.61 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances2014201520162017201820192020202120220255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Gilbert Saratoga, US 10 85

Cited Art Landscape

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Patent Citation Ranking

  • 13 Citation Count
  • H01R Class
  • 77.04 % this patent is cited more than
  • 10 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges312180240011545241465741001 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +01002003004005006007008009001000110012001300140015001600170018001900

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