COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH ACTIVE REGION WITH RELAXED COMPRESSION STRESSES, AND FABRICATION METHOD
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United States of America Patent
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app pub date -
May 18, 2015
filing date -
Jun 13, 2013
priority date (Note) -
Abandoned
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Abstract
An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by a trench insulating region. The transistor, active region and trench insulating region are covered by an additional insulating region. A metal contact extends through the additional insulating region to make contact with the trench insulating region. The metal contact may penetrate into the trench insulating region.
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