SPLIT-GATE FLASH MEMORY EXHIBITING REDUCED INTERFERENCE
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United States of America Patent
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app pub date -
May 20, 2015
filing date -
Jul 25, 2011
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Abandoned
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Abstract
A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.
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