MEMORY TESTING AND FAILURE DATA FILTERING
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United States of America Patent
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N/A
Issued Date -
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app pub date -
Mar 26, 2014
filing date -
Mar 10, 2014
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A method for evaluating test results for a memory module. Contents of a data stream are reviewed for one or more sections of the memory module. A plurality of counters is incremented when a defective portion is encountered in the data stream for a first section of the memory module. Values of the plurality of counters are compared to corresponding threshold values. Provided two or more counter values are at or above their threshold values, the first section is marked as bad, all defective portions of the first section are removed from the test data stream, and a failure header indicating that the first section is bad is stored and because of which counters in an error cache, otherwise each defective portion of the first section is marked as good in the data stream provided an error correction counter value of the plurality of counter values is equal to or below a first threshold value. Data from the data stream identifying defective portions of the first section are stored in an error cache for each remaining defective portion of the first section identified after the error correction counter value passes the first threshold value.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
ADVANTEST CORPORATION | 1-6-2 MARUNOUCHI CHIYODA-KU TOKYO 100-0005 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
HYDER, Matt | Boise, US | 2 | 9 |
KRECH,, JR Alan S | Fort Collins, US | 6 | 21 |
LAI, Ken Hanh Duc | Sunnyvale, US | 6 | 31 |
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11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Mar 10, 2027 |
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