On-chip analog-to-digital converter (ADC) linearity text for embedded devices
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United States of America Patent
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Jan 19, 2016
Grant Date -
Sep 3, 2015
app pub date -
Feb 28, 2014
filing date -
Feb 28, 2014
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Abstract
A method for testing linearity of an ADC, comprising receiving a trigger signal indicating an ADC input voltage step adjustment, reading an ADC output sample upon receiving the trigger signal, wherein the ADC output sample has a value range of N integer values that correspond to N discrete ADC output codes, computing a histogram of code occurrences for M consecutive ADC output codes, wherein the histogram comprises M number of bins corresponding to the M consecutive ADC output codes, and wherein M is less than N, updating a DNL value and an INL value according to the histogram at an interval of K number of ADC output sample readings, and shifting the histogram by one ADC output code after updating the DNL and the INL values.
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