ELECTROSTATIC DISCHARGE CIRCUIT WITH REDUCED STANDBY CURRENT
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United States of America Patent
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Issued Date -
Sep 3, 2015
app pub date -
Feb 28, 2014
filing date -
Feb 28, 2014
priority date (Note) -
Abandoned
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Abstract
Techniques for reducing leakage current during normal operation of an electrostatic discharge (ESD) circuit are described herein. In one embodiment, a circuit comprises an internal circuit and an electrostatic discharge (ESD) rail clamp coupled in parallel to the internal circuit and between first and second power supply rails. The ESD rail clamp is operable to shunt ESD current from the first power supply rail to the second power supply rail via a low resistance shunt path. The ESD rail clamp comprises an ESD trigger circuit configured to detect an ESD event and a plurality of discharging transistors coupled in series. The ESD trigger circuit is configured to turn off the discharging transistors during normal operation and to turn on the discharging transistors to form the low resistance shunt path in response to detection of the ESD event.
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