Method for manufacturing a monolithic silicon wafer comprising multiple vertical junctions
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United States of America Patent
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Feb 27, 2018
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Sep 3, 2013
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Sep 4, 2012
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Abstract
The present invention relates to a method for manufacturing a monolithic silicon wafer (10) comprising multiple vertical junctions (2) having an alternation of n-doped areas and p-doped areas, including at least the steps of: (i) providing a liquid bath (100) including silicon, at least one n-type doping agent and at least one p-type doping agent; (ii) proceeding to directionally solidify the silicon in a direction (I), varying the convection-diffusion parameters thereof in order to alternate the growth of n-doped silicon layers (101) and p-doped silicon layers (102); and (iii) cutting a slice (104), parallel to the direction (I), of the multi-layer structure obtained at the end of the step (ii), such as to obtain said expected wafer (10).
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