Three dimensional circuit including shielded inductor and method of forming same
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United States of America Patent
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Jan 17, 2017
Grant Date -
Sep 3, 2015
app pub date -
May 15, 2015
filing date -
Sep 25, 2013
priority date (Note) -
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Abstract
The three dimensional (3D) circuit includes a first tier including a semiconductor substrate, a second tier disposed adjacent to the first tier, a three dimensional inductor including an inductive element portion, the inductive element portion including a conductive via extending from the first tier to a dielectric layer of the second tier. The 3D circuit includes a ground shield surrounding at least a portion of the conductive via. In some embodiments, the ground shield includes a hollow cylindrical cage. In some embodiments, the 3D circuit is a low noise amplifier.
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