Multi-port memory cell
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United States of America Patent
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Feb 9, 2016
Grant Date -
Sep 3, 2015
app pub date -
Feb 28, 2014
filing date -
Feb 28, 2014
priority date (Note) -
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Abstract
A circuit includes a first data line, a second data line, a reference node, and a memory cell. The reference node is configured to have a reference voltage level corresponding to a first logical value. The memory cell includes a data node, a first transistor and a second transistor connected in series between the first data line and the reference node, and a third transistor between the data node and the second data line. A gate of the first transistor is coupled to the data node, and the first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value.
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