Memory reading circuit, memory device and method of operating memory device
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United States of America Patent
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Nov 8, 2016
Grant Date -
Sep 3, 2015
app pub date -
Feb 28, 2014
filing date -
Feb 28, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
A circuit for reading a memory device includes a sense amplifier (SA) and a controller. The SA has an input, an output and an enabling terminal. The controller has a first input coupled to the output of the SA, a second input configured to receive a control signal, and an output coupled to the enabling terminal of the SA to send an SA enabling (SAE) signal from the controller to the SA. The controller is configured to start the SAE signal, in response to the control signal, to enable the SA, and to terminate the SAE signal, in response to an SA output signal at the output of the SA, to disable the SA.
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Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | May 8, 2028 |
