DELAY-LOCKED LOOP WITH DUAL LOOP FILTERS FOR FAST RESPONSE AND WIDE FREQUENCY AND DELAY RANGE
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United States of America Patent
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Issued Date -
Aug 7, 2014
app pub date -
Mar 31, 2014
filing date -
Dec 20, 2011
priority date (Note) -
Abandoned
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Abstract
A delay-lock loop includes two feedback loops for controlling delay elements in the delay-lock loop. The first feedback loop includes a feedback circuit for generating a feedback signal indicating a delay adjustment based on a phase difference between an input clock signal to the delay-locked loop and an output clock signal generated by the delay-locked loop. The second feedback loop includes a power regulator that generates a regulated signal by regulating a power supply using the feedback signal as a reference. The delay-lock loop further includes a variable delay circuit including a resistor-capacitor network. The variable delay circuit controls a capacitance in the resistor-capacitor network based on the feedback signal and controls a resistance of the resistor-capacitor network based on the regulated signal. In this way, variable delay circuit generates the output clock signal by delaying the input clock signal based on both the feedback signal and the regulated signal.
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