Efficient drift avoidance mechanism for synchronous and asynchronous digital sample rate converters
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United States of America Patent
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Dec 8, 2015
Grant Date -
Aug 27, 2015
app pub date -
Feb 4, 2015
filing date -
Feb 5, 2014
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Abstract
A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.
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