Bias circuits and methods for stacked devices
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United States of America Patent
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Feb 2, 2016
Grant Date -
Aug 27, 2015
app pub date -
Jun 6, 2014
filing date -
Feb 27, 2014
priority date (Note) -
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Abstract
Embodiments of the present disclosure include a bias circuit for generating bias voltages to stacked transistors. In one embodiment, stacked transistors are coupled between an input transistor and an output node. A modulated power supply voltage and an input signal produce a voltage at the output node. The modulated power supply voltage is provided as an input to the bias circuit. Bias voltages are generated that change with the power supply voltage. In one embodiment, particular transistors in the stack are biased so that their control terminals are effectively short circuited when the power supply voltage is reduced.
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