ACCELERATION SYSTEM IN 3D DIE-STACKED DRAM

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United States of America Patent

APP PUB NO 20150242308A1
SERIAL NO

14610040

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Provided is a memory device including a logic layer including at least one of a peripheral device, an interface, and a built-in self-test (BIST) module and a reconfigurable accelerator (RA), and at least one data layer to store data, wherein the RA is positioned in a vacant space of the logic layer and processes at least a portion of a task processed by the memory device.

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Patent Owner(s)

Patent OwnerAddress
UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)50 UNIST-GIL ULSAN 44919

International Classification(s)

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  • 2015 Application Filing Year
  • H01L Class
  • 25498 Applications Filed
  • 22451 Patents Issued To-Date
  • 88.06 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances20152016201720182019202020212022202320240255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
KIM, Yong Joo Daejeon, KR 56 465
LEE, Jin Yong Seoul, KR 63 200
LEE, Jong Eun Ulsan, KR 10 31
PAEK, Yun Heung Seoul, KR 3 20

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Patent Citation Ranking

  • 10 Citation Count
  • H01L Class
  • 10.46 % this patent is cited more than
  • 10 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges1377800619237183722181459473474314501 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05001000150020002500300035004000450050005500600065007000750080008500

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