Delay locked loop and semiconductor apparatus
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United States of America Patent
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Jul 19, 2016
Grant Date -
Aug 20, 2015
app pub date -
May 4, 2015
filing date -
Dec 24, 2012
priority date (Note) -
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Abstract
A delay locked loop includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a delay locked loop clock signal; a delay model unit configured to delay the delay locked loop clock signal by a modeled delay value and output delayed delay locked loop clock signal as a feedback clock signal; a calculation code generation unit configured to convert a phase of the reference clock signal and a phase of the feedback clock signal into a first code and a second code, respectively, and perform a calculation on the first and second codes so as to generate a calculation code; and a delay code generation unit configured to control the delay code in response to the calculation code.
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