Pre-program of clock generation circuit for faster lock coming out of reset
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United States of America Patent
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Mar 22, 2016
Grant Date -
Aug 20, 2015
app pub date -
Feb 14, 2014
filing date -
Feb 14, 2014
priority date (Note) -
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Abstract
A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.
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