INTERFACE ANALYSIS FOR VERIFICATION OF DIGITAL CIRCUITS
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United States of America Patent
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Issued Date -
Aug 20, 2015
app pub date -
Feb 18, 2014
filing date -
Feb 18, 2014
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Abandoned
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Abstract
A method for performing an interface analysis. The method includes identifying a first module included in a representation of a digital circuit. The method also includes identifying a first output port associated with the first module. The method further includes identifying a first logic path that extends from the first output port. The method also includes determining that the first logic path extends to a first storage element included in the first module. The method further includes including the first module, the first output port, the first logic path, and the first storage element in interface logic output data.
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