SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
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United States of America Patent
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Issued Date -
Aug 6, 2015
app pub date -
Jan 22, 2015
filing date -
Feb 3, 2014
priority date (Note) -
Abandoned
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Abstract
Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.
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