ABRIDGED ERASE VERIFY METHOD FOR FLASH MEMORY
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United States of America Patent
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Issued Date -
Aug 6, 2015
app pub date -
Feb 6, 2014
filing date -
Feb 6, 2014
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A non-volatile memory device includes a control circuit configured to perform a block erase operation including a block erase cycle and an erase verify cycle on a block of memory cells. The control circuit is configured to perform the erase verify cycle by storing a last verify address for each sector of the block of memory cells, verifying each memory cell in a sector starting from the last verify address for the sector until a memory cell has failed erase verification in that sector, storing the memory cell address of the failed memory cell as the last verify address for that sector, skipping the erase verification for the remaining memory cells in that sector, and continuing the erase verify cycle at a last verify address for the next sector.
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