METHOD FOR MANAGING FLASH MEMORIES HAVING MIXED MEMORY TYPES USING A FINELY GRANULATED ALLOCATION OF LOGICAL MEMORY ADDRESSES TO PHYSICAL MEMORY ADDRESSES
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United States of America Patent
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Issued Date -
Aug 6, 2015
app pub date -
Apr 29, 2014
filing date -
Jan 31, 2014
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Abstract
A method manages a flash memory for a computer system having flash chips divided into separately erasable physical memory blocks with a limited maximum erasure frequency. The memory blocks are divided into writable pages being subdivided into addressable subpages. The subpages are addressed by a computer via logical sector addresses being converted into physical subpage addresses. The flash memory has a first area containing single-level flash chips with a higher maximum erasure frequency, and a second area containing multi-level flash chips with a lower maximum erasure frequency. If write operations in the first area exceed an upper threshold for a filling level of written memory blocks, a written memory block having a low erasure counter is searched for in the first area, whose valid subpages are transferred into a memory block of the second area. The address allocations for the transferred subpages are updated.
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