Byte Erasable Non-volatile Memory Architecture And Method Of Erasing Same
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United States of America Patent
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Issued Date -
Jul 30, 2015
app pub date -
Jan 27, 2014
filing date -
Jan 27, 2014
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Abstract
Memory cells arranged in rows and columns, each with source and drain regions of equal breakdown voltages, and floating and control gates over the channel region. The memory cell rows are arranged in clusters each with a source line connecting all the source regions in just that cluster. Word lines each connect all the control gates for a row of memory cells. Bit lines each connect all the drain regions for a column of memory cells. Source line interconnects each connect all the source lines for a column of clusters. One cluster is erased by applying a positive voltage to a word line for that cluster and ground potential to other word lines, ground potential to the source line interconnect for that cluster and a positive voltage to other source line interconnects, and ground potential to the bit lines for that cluster and a positive voltage to other bit lines.
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