PARTITIONED RESISTIVE MEMORY ARRAY
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United States of America Patent
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Issued Date -
Jul 30, 2015
app pub date -
Jan 30, 2014
filing date -
Jan 30, 2014
priority date (Note) -
Abandoned
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Abstract
A resistive memory array partitioned into a plurality of memory units is disclosed. Each memory unit includes a plurality of resistive memory elements, a plurality of row lines, a plurality of column lines, a plurality of row select switching devices, and a plurality of column select switching devices. Each resistive memory element is in communication with one of the row lines and one of the column lines. Each row line is in communication with a corresponding one of the row select switching devices. Each column line is in communication with a corresponding one of the column select switching devices.
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