VERIFICATION METHOD AND VERIFICATION APPARATUS

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United States of America Patent

APP PUB NO 20150205908A1
SERIAL NO

14592597

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A verification apparatus detects a first delay circuit connected to an output side of a second isolator in a first netlist including first and second isolators, in which the first isolator is inserted into a first path between first and second power domains under first rule, and the second isolator is inserted into a second path between the first and third power domains under second rule. To verify whether the first and second isolators are inserted under the first and second rules respectively, the verification apparatus searches a second netlist generated by performing an optimization step including delay adjustment on the first netlist for a connection destination of the first power domain, and if the connection destination is not the first delay circuit, continues searching, and detects the second power domain, to thereby specify the first path at the time of the first rule being applied.

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Patent Owner(s)

Patent OwnerAddress
SOCIONEXT INCKANAGAWA KANAGAWA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
IWAKI, Yoshitoshi Akiruno, JP 1 0

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