DESIGN METHOD AND DESIGN APPARATUS
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United States of America Patent
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Issued Date -
Jul 23, 2015
app pub date -
Jan 9, 2015
filing date -
Jan 20, 2014
priority date (Note) -
Abandoned
status (Latency Note)
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Abstract
A design apparatus preferentially selects a low coefficient in a range in which design conditions are met from a group of coefficients (coefficient library) indicative of an increase in delay time at the time of voltage drop for combinations of one of a plurality of clock buffers which differ in parameter and one of a plurality of wiring loads, which differ in parameter, connected to the one of the plurality of clock buffers, selects from the plurality of clock buffers and the plurality of wiring loads a clock buffer and a wiring load each having a parameter associated with the selected coefficient, and designs a clock path.
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