CONTACT RESISTANCE REDUCTION IN FINFETS

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United States of America Patent

SERIAL NO

14658898

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A semiconductor device having fin transistors includes a plurality of substantially parallel semiconductor fins formed over a substrate and a gate structure formed over the fins transversely to a longitudinal axis of the fins. Source and drain regions are formed on opposite sides of the gate structure and are merged with the fins by an epitaxially grown crystalline material between the fins in merged regions. Interface layers are formed on the fins in regions disposed apart from both sides of the gate structure. The interface layers are formed over a top and at least a portion of opposing sides of the fins. Contact lines are formed over the interface layers such that contact is made at the top surface of the interface layer on the fins and at least a portion of the sides of the interface layer on the fins.

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Patent Owner(s)

Patent OwnerAddress
GLOBALFOUNDRIES INCPO BOX 309 UGLAND HOUSE GRAND CAYMAN KY1-1104

International Classification(s)

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  • 2015 Application Filing Year
  • H01L Class
  • 25498 Applications Filed
  • 22451 Patents Issued To-Date
  • 88.06 % Issued To-Date
Click to zoom InYear of Issuance% of Matters IssuedCumulative IssuancesYearly Issuances20152016201720182019202020212022202320240255075100

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
BASKER, VEERARAGHAVAN S SCHENECTADY, US 494 4609
LIU, QING GUILDERLAND, US 537 5415
YAMASHITA, TENKO SCHENECTADY, US 610 5507
YEH, CHUN-CHEN CLIFTON PARK, US 417 3749

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Patent Citation Ranking

  • 2 Citation Count
  • H01L Class
  • 10.46 % this patent is cited more than
  • 10 Age
Citation count rangeNumber of patents cited in rangeNumber of patents cited in various citation count ranges1377800619237183722181459473474314501 - 1011 - 2021 - 3031 - 4041 - 5051 - 6061 - 7071 - 8081 - 9091 - 100100 +05001000150020002500300035004000450050005500600065007000750080008500

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