METHOD OF CONTROLLING MEMORY ARRAY
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United States of America Patent
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Issued Date -
Jul 9, 2015
app pub date -
Dec 22, 2014
filing date -
Jan 9, 2014
priority date (Note) -
Abandoned
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Abstract
A method of controlling a memory array is provided. The memory array includes memory cells, first control lines, second control lines, parallel bit lines and word lines that are perpendicular to the bit lines and are electrically insulated therefrom. The method includes selecting one or more of the memory cells and enabling a reading, a programming or an erasing operation on the selected memory cell(s) by applying different voltages respectively to word line(s), first control line(s) and second control line(s), connected to the selected memory cell(s), bit line(s) connected to source(s) of the selected memory cell(s) and bit line(s) connected to drain(s) of the selected memory cell(s), wherein the remaining one(s) of the first and second control line(s) that are connected to the unselected one(s) of the memory cell(s), is applied with a minus voltage ranging from −3 V to −0.5 V.
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