MEMORY SYSTEM WITH HIGH PERFORMANCE AND HIGH POWER EFFICIENCY AND CONTROL METHOD OF THE SAME
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United States of America Patent
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Issued Date -
Jul 9, 2015
app pub date -
Jan 9, 2014
filing date -
Jan 9, 2014
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Abandoned
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Abstract
A memory control system has an SDRAM device, a memory controller, a loading monitoring unit and a memory physical module. The SDRAM device has a plurality of SDRAM cells for storing data. The loading monitoring unit detects workload of a memory interface of the SDRAM device. The memory controller switches an operation condition of the memory system from a first condition to a second condition when the detected workload satisfies at least one predetermined criterion. The memory physical module is coupled between the SDRAM device and the memory controller and has an interface timing calibration circuit configured to adjust timing of signals of the memory interface such that the signals are adjusted in best timing location and data are captured with a great timing margin.
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