MEMORY AND READING METHOD THEREOF, AND CIRCUIT FOR READING MEMORY
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United States of America Patent
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Issued Date -
Jul 9, 2015
app pub date -
Dec 29, 2014
filing date -
Jan 7, 2014
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Abstract
Memory and reading method thereof, and circuit for reading memory are provided. The memory includes a memory array; a row decoding circuit configured to apply word line voltage to selected word line in reading operation; a column decoding circuit configured to select a source line connected with a target memory cell based on reading data, the target memory cell using the selected word line; and a reading circuit including first and second input terminals and a comparison node, the first input terminal being connected with the source line of the memory cell through the column decoding circuit and configured to let in reading current of the target memory cell, the second input terminal being configured to let in base current, the comparison node being configured to compare reading current with reference current related to the base current to output reading result. The memory is driven under low voltage.
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