Memory system including PE count circuit and method of operating the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Jul 17, 2018
Grant Date -
Jul 2, 2015
app pub date -
Dec 27, 2013
filing date -
Dec 27, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
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US Family Size
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Non-US Coverage
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Abstract
A memory system includes a memory device. The memory device includes a substrate. A memory array defines a plurality of pages, each page including a data area for storing data and a spare area for storing a program/erase (PE) count value, the PE count value indicating a number of PE cycles performed on the page. A PE count circuit is configured to perform a PE count read operation on a target page. A host determines whether to perform a data write operation on the target page or another PE count read operation on a new target page based on a result of the PE count read operation. PE cycles of a page are controlled by the PE count read operation. The memory array and the PE count circuit are formed in different layers of the substrate.
First Claim
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International Classification(s)
- 2013 Application Filing Year
- G06F Class
- 48303 Applications Filed
- 43929 Patents Issued To-Date
- 90.95 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- G06F Class
- 0 % this patent is cited more than
- 7 Age
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Jan 17, 2026 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Jan 17, 2030 |
