INTEGRATED CIRCUIT PACKAGING SYSTEM WITH VIALESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOF
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United States of America Patent
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Jun 25, 2015
app pub date -
Dec 20, 2013
filing date -
Dec 20, 2013
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Abstract
A system and method of manufacture of an integrated circuit packaging system includes: a trace layer; a stud directly on a portion of the trace layer for forming a metal-to-metal connection with the trace layer; a dielectric layer directly on the trace layer and the stud for forming a vialess substrate exposing the trace layer and the dielectric layer; an active device on the trace layer, the trace layer exposed from the vialess substrate; a die interconnect coupled between the active device to the trace layer for providing electrical connectivity; and an external interconnect connected to the stud for electrically coupling the active device, the trace layer, the studs, and the external interconnect.
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