Method and Layer Structure for Preventing Intermixing of Semiconductor Layers
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United States of America Patent
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Jun 18, 2015
app pub date -
Nov 21, 2014
filing date -
Sep 17, 2010
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Abandoned
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Abstract
A semiconductor device includes an etch-stop layer between a first layer of a field-effect transistor and a second layer of a bipolar transistor, each of which includes at least one arsenic-based semiconductor layer. A p-type layer is between the second layer and the etch-stop layer, and the device can include an n-type layer deposited between the etch-stop layer and p-type layer. The p-type layer provides an electric field that inhibits intermixing of the InGaP layer with layers in the first and second layers.
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