PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME
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United States of America Patent
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Issued Date -
Jun 18, 2015
app pub date -
Dec 11, 2014
filing date -
Dec 12, 2013
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Abstract
A package assembly and a method for manufacturing the same are disclosed. The package assembly includes a chip carrier having interconnect areas, solder disposed in the interconnect areas, and an electronic device having conductive bumps each of which has an end in contact with the solder. Thus, the electronic device is soldered to the chip carrier. The interconnect areas each have a recess for contacting and receiving the solder and securing respective one of the conductive bumps. When the solder flows during operation, the package assembly according to the present disclosure maintains a good electrical connection between the chip carrier and the electronic device, which results in a high reliability and a long lifetime.
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