LDMOS DEVICE WITH IMPROVED AVALANCHE ENERGY AND ASSOCIATED FABRICATING METHOD
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United States of America Patent
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app pub date -
Feb 13, 2015
filing date -
Jun 28, 2013
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Abandoned
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Abstract
A semiconductor device has: a gate region having a dielectric layer and a conducting layer; an N-type drain region having a lightly doped drift region and a highly doped drain contact region formed in the drift region, wherein the drain region is at a first side of the gate region; a P-type body region adjacent to the drain region, the body region having a lightly doped first portion body region, a second portion body region, and a highly doped body contact region; and an N-type highly doped source region in the body region, wherein the source region is at a second side of the gate region; wherein the first portion body region is doped with boron, the second portion body region is doped with boron and indium in the first portion body region, and the second portion body region is located adjacent to and beneath the source region.
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