CONTENTION MANAGEMENT FOR A HARDWARE TRANSACTIONAL MEMORY
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United States of America Patent
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Issued Date -
Jun 4, 2015
app pub date -
Feb 10, 2015
filing date -
Nov 21, 2007
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Abstract
A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.
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