Method of forming and structure of a non-volatile memory cell
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United States of America Patent
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May 21, 2015
app pub date -
Jan 26, 2015
filing date -
Sep 27, 2013
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Abstract
A structure of a memory cell includes a substrate, a well, three source/drain doped regions, two bottom dielectric layers, two charge trapping layers, a blocking layer and two gates to form a storage transistor and a select transistor of the memory cell. A bottom dielectric layer and a charge trapping layer may be used to provide the dielectric of the gate of the select transistor with enough thickness but without any additional fabrication process.
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