Oscillator Buffer and Method for Calibrating the Same
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United States of America Patent
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Issued Date -
May 21, 2015
app pub date -
Nov 13, 2014
filing date -
Nov 13, 2013
priority date (Note) -
Abandoned
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Abstract
A buffering circuit for buffering an oscillator signal. The buffering circuit includes a plurality of PMOS and NMOS transistor pairs connected in parallel, each pair having connected gate terminals and connected drain terminals forming an inverter circuit, each pair arranged for receiving via a direct coupling an oscillator signal at its gate terminal, and each pair further being connected with an additional PMOS and NMOS transistor. The buffering circuit also includes a control circuit arranged for receiving an output signal provided by the inverter circuits, for deriving information on the DC level of the output signal, and for adjusting a voltage transfer curve expressing a relationship between a voltage at the input and output of the buffering circuit, by switching on or off the additional PMOS and NMOS transistors based on the derived information
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