Oscillator Buffer and Method for Calibrating the Same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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N/A
Issued Date -
May 21, 2015
app pub date -
Nov 13, 2014
filing date -
Nov 13, 2013
priority date (Note) -
Abandoned
status (Latency Note)
Importance
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US Family Size
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Non-US Coverage
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Abstract
A buffering circuit for buffering an oscillator signal. The buffering circuit includes a plurality of PMOS and NMOS transistor pairs connected in parallel, each pair having connected gate terminals and connected drain terminals forming an inverter circuit, each pair arranged for receiving via a direct coupling an oscillator signal at its gate terminal, and each pair further being connected with an additional PMOS and NMOS transistor. The buffering circuit also includes a control circuit arranged for receiving an output signal provided by the inverter circuits, for deriving information on the DC level of the output signal, and for adjusting a voltage transfer curve expressing a relationship between a voltage at the input and output of the buffering circuit, by switching on or off the additional PMOS and NMOS transistors based on the derived information
First Claim
Other Claims data not available
Family
| Country | kind | publication No. | Filing Date |
|---|---|---|---|
| EP | A1 | EP2874042 | Nov 13, 2013 |
| JP | A | JP2015095900 | Nov 04, 2014 |
International Classification(s)
- 2014 Application Filing Year
- H03L Class
- 712 Applications Filed
- 648 Patents Issued To-Date
- 91.02 % Issued To-Date
Cited Art Landscape
Patent Citation Ranking
- 3 Citation Count
- H03L Class
- 7.07 % this patent is cited more than
- 10 Age