SYSTEM-LEVEL TESTING OF NON-SINGULATED INTEGRATED CIRCUIT DIE ON A WAFER
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United States of America Patent
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Issued Date -
Apr 23, 2015
app pub date -
Oct 22, 2013
filing date -
Oct 22, 2013
priority date (Note) -
Abandoned
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Abstract
Structures and methods for system-level testing of integrated circuit dies at wafer sort is disclosed. This concept combines a system-level test (which is traditionally a “socketed” test performed on a packaged IC in a test socket) with the ability to contact an integrated circuit die on a wafer using a probe card. The die on the wafer becomes part of the system-level environment in order to test the integrated circuit die in the system-level environment prior to packaging, and may be used to better identify known good die.
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