METHOD FOR THE FORMATION OF CMOS TRANSISTORS

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United States of America Patent

APP PUB NO 20150093861A1
SERIAL NO

14042884

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Abstract

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An SOI substrate includes first and second active regions separated by STI structures and including gate stacks. A spacer layer conformally deposited over the first and second regions including the gate stacks is directionally etched to define sidewall spacers along the sides of the gate stacks. An oxide layer and nitride layer are then deposited. Using a mask, the nitride layer over the first active region is removed, and the mask and oxide layer are removed to expose the SOI substrate in the first active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the first active region and a protective nitride layer is deposited. The masking, nitride layer removal, and oxide layer removal steps are then repeated to expose the SOI in the second active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the second active region.

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Patent Owner(s)

Patent OwnerAddress
STMICROELECTRONICS INC750 CANYON DRIVE SUITE 300 COPPELL TX 75019

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Khare, Prasanna Schenectady, US 56 716
Liu, Qing Guilderland, US 537 5415
Loubet, Nicolas Guilderland, US 245 2330

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